3D-TSV: The 3D trajectory-based stress visualizer

TSV-Based 3D Integration

Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose plac...

Research Needs for TSV-Based 3D IC Architectural Floorplanning

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architect...

TSV Multiplexing: A 3D NoC Occupancy Analysis

Networks-on-chip (NoCs) are proposed as promising packet-based communication platforms for multi-processor system-on-chip (MPSoC) design, due to scalability, better throughput and reduced power consumption [1]. NoC-based architectures are characterized by various trade-offs with regard to structural characteristics, performance specifications, and application demands. However, increasing the nu...

The Information Visualizer: A 3D User Interface for Information Retrieval

Loop Parallelization using the 3D Iteration Space Visualizer

A 3D iteration space visualizer (ISV) is presented to analyze the parallelism in loops and to find loop transformations which enhance the parallelism. Using automatic program instrumentation, the iteration space dependency graph (ISDG) is constructed, which shows the exact data dependencies of arbitrarily nested loops. Various graphical operations such as rotation, zooming, clipping, coloring a...